Ayar Labs launches the industry’s first universal chiplet Interconnect Express (UCIE) optical interconnect Chiplet, designed specifically to maximize AI infrastructure performance and efficiency while reducing latency and power consumption of large-scale AI workloads.
This breakthrough will help meet the growing demand for advanced computing architectures, especially as AI systems continue to scale. By combining UCIE electrical interfaces, the new Chiplet is designed to eliminate data bottlenecks while seamlessly integrating with chips from different vendors, thus facilitating a more accessible and cost-effective ecosystem with advanced optical technologies.
The Chiplet, called Teraphy™, enables 8 TBPS bandwidths and is powered by Ayar Labs’ 16-wavelength Supernova™ light source. This optical interconnection technology is designed to overcome the limitations of traditional copper interconnections, especially for data-intensive AI applications.
“Optical interconnects are needed to solve the power density challenges in large-scale AI fabrics,” said Mark Wade, CEO of Ayar Labs.
Integration with UCIE standards is particularly important because it allows chiplets from different manufacturers to work seamlessly. This interoperability is crucial to the future of chip design, which is increasingly moving towards a multi-vendor modular approach.
UCIE Standard: Create an open chipmunk ecosystem
The UCIE consortium that developed standards aims to build an “open ecosystem of chiplets for packaging innovation”. Their universal Chiplet Interconnect Express specification addresses the industry’s need for more customizable packaging-grade integration by combining high-performance molds with DIE interconnect technology with multi-vendor interoperability.
“Advances in UCIE standards mark a significant advance in building more integrated and effective AI infrastructures due to the interoperable chiplet ecosystem,” said Dr. Debendra Das Sharma, president of the UCIE Alliance.
The standard creates a universal interconnect at the packaging level, allowing chip designers to mix components from different vendors to create more professional and efficient systems. The UCIE Alliance recently announced its UCIE 2.0 specification release, indicating the continued development and improvement of the standard.
Industry support and meaning
The announcement has been strongly recognized by major players in the semiconductor and AI industries for all members of the UCIE consortium.
Mark Papermaster from AMD highlights the importance of open standards: “The strong, open and vendor-neutral chip ecosystem provided by UCIE is critical to meeting the challenges of scaling network solutions.
Kevin Soukup from GlobalFoundries responded to this sentiment, noting that “As the industry transitions to Chip-based chiplet-based system allocation approaches, the UCIE interface for chiplet-to-chip communication is rapidly becoming the de facto fact, and we are pleased to see Ayar Labs show pivical Facefles, Pivotals, Pivotals, Pivotals” with the criteria for choosing UCIE networks.
Technology advantages and future applications
The convergence of UCIE and optical interconnections represents a paradigm shift in the computing architecture. By combining silicon photonics with the UCIE standard, the technology allows GPUs and other accelerators to “communicate between distances from millimeters to kilometers while effectively functioning as a single giant GPU.”
The technology also facilitates co-packaging optics (CPO), a multinational manufacturing company Jabil has demonstrated a model with Ayar Labs’ light source, which is capable of “up to PETABIT per second of bidirectional bandwidth”. This approach promises higher compute density per rack, enhanced cooling efficiency, and support for thermal S-type functionality.
“Co-packaged optical (CPO) chips will change the way we address data bottlenecks in large-scale AI computing,” said Lucas Tsai of Taiwan Semiconductor Manufacturing Corporation (TSMC). “The availability of UCIE optical chips will promote a strong ecosystem, ultimately promoting wider adoption and continuous innovation across the industry.”
Change the future of computing
As AI workloads continue to grow in complexity and scale, the semiconductor industry is increasingly using chiplet-based architectures as a more flexible and collaborative approach to chip design. The introduction of Ayar Labs’ first UCIE optical chip solves bandwidth and power consumption challenges that have become bottlenecks for high-performance computing and AI workloads.
The combination of open UCIE standards and advanced optical interconnect technology is expected to revolutionize system-level integration and drive the future of scalable, efficient computing infrastructure, especially the demanding requirements for next-generation AI systems.
Strong industry support for this development demonstrates the potential of a rapidly expanding ecosystem of UCIE-compatible technologies, which could accelerate innovation across the semiconductor industry while making advanced optical interconnect solutions wider and more cost-effective.
